The only difference is the outputs being available 'immediately' or at the next clock edge. Neither solution is really a way of 'reducing processing time' because the same logic is required to implement whatever function you create and the delay through that logic would be the same. If you want to store the results of your design to prevent changes to them if there is a change or glitch on the inputs, you would need to have a synchronous design. In other words, your design is purely 'sensitive' to the inputs because the outputs will immediately (after a logic gate delay) change if there is a change to the inputs. If your outputs are constantly monitored by whatever they are being fed to and whatever that is can process constantly changing inputs to your design (like just simple LEDs), the design can be purely combinational. So the answer really depends on what you need. So your question really is whether to implement your design as either a pure combinational logic structure (composed of just LUTs) or a synchronous design where outputs, generated from LUT logic, are stored in registers. What you are thinking of in your second paragraph are the registers that are part of the LABs (logic array blocks) to store data. They are not a different type of resource in the device. Thus one of the most important phases of the FPGA CAD ow is the technology mapping step that maps an optimized circuit description into a LUT network present in the target FPGA architecture. I am using a Cyclone IV device and Quartus software.Īn encoder is a logic structure constructed from LUTs (look up tables). The number of LUTs needed to implement a given circuit de- termines the size and cost of the FPGA-based realization. Please suggest me whether to use an encoder or LUT if the main aim of the design is to reduce the processing time. If we use a lookup table and store the data, the data will be available as soon as we provide the clock signal and it won't require additional delay like encoder. The 3-bit output value can be stored in the LUT corresponding to the a given input.

The 5-bit input In can be used as the address for LUT and the storage size of LUT will be 3 bit to store the output Out. I can also use a lookup table (LUT) which has 32 locations. However, using an encoder will introduce an additional delay. I can design this using a 8x3 Encoder in which 5 out of 8 inputs can be connected to In to provide the corresponding output, and other inputs (3 out of 8 inputs of encoder) can be set to 0. I want to design a circuit in which a 5-bit input In (ranges from 0 to 31) is associated with a corresponding 3-bit output Out.

Fpga lut circuit